Re: Programming Languages

On Sun, 3 Nov 2024 20:53:19 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 3/11/2024 7:56 pm, Cursitor Doom wrote:

On Sun, 3 Nov 2024 13:27:26 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
 

On 3/11/2024 6:21 am, Cursitor Doom wrote:

On Sat, 2 Nov 2024 13:07:32 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
>

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vg4fff$3lok1$1@dont-email.me...

On 2/11/2024 12:01 pm, Edward Rawde wrote:

"Cursitor Doom" <cd999666@notformail.com> wrote in message news:vg3575$3bio0$1@dont-email.me...

>
<snip>
>

You've also got the point that when there's a voltage drop across the FET channel, it adds to the gate-to-channel voltage (as has
been mentioned here) and you can cancel that with an in-phase fundamental component

>
The last circuit of my own had both an n fet and a p fet.
I found that by adding a capacitor from one gate to the other (to try to cancel the unwanted signals in opposite phase) I could get
the unwanted gate signal below 100uV. I then had harmonics approaching 60dB down except one at 50dB (I think 2KHz). Not brilliant
but not bad.
>
There are some useful pointers here:
https://sound-au.com/articles/sinewave.htm
In particular where it says "Done properly, a JFET can provide distortion performance that is as good or better than a lamp or
thermistor."
>
Perhaps I'll concentrate on how to make the FET behave as a voltage variable resistor over the widest possible range.
>
I also what to look into what I meant by crud and non crud mode in LTSpice.

>

This mysterious effect can depend on things such as which specific computer is used and how long is specified before collecting
simulation data.

>
John May made the point that in LTSpice trapezium integration (as
opposed to modified trapezium integration) give less distortion in the
simulated waveform. Numerical integration is a good way of accumulating
rounding error, and shorter words mean more rounding error.
>

You can see it in the gate voltage after startup. It looks a bit like a PLL hunting and eventually locking but it doesn't happen at
startup, it happens after seconds.

>
Closed loop feedback takes a while to settle. If you known what you are
doing you can mostly make the settling dead-beat, but sometimes this
costs you more performance that you can afford.
>

So I'll need to be able to post some pictures to show that. I'll get to that.

>
<snipped Cursitor Doom being an ass>
>

Of course it is.That's why Wein bridges need a non-linear element that
can be adjust to get the gain exactly right and keep it there.

 
Not necessarily. You could have a linear component set up in such a
way that it performs non-linearly.

>
Then it stops being a linear component.
>

Is there an easy way to remove a DC offset from a simulation trace so that my n and p gate signals can be superimposed after
startup?

>
There is but Cursitor Doom doesn't know it.

 
Yeah, still haven't heard of capacitors.

>
Non sequitur. The simulation program involved - LTSpice - does
accommodate capacitors, but you don't need to add them to the circuit
being simulated to do what Edward Rawde was asking for.

The fact is that a 1fF cap would have had the desired effect without
compromising the circuit's performance. Why do you feel the need to
complicate everything? Oh yes, to show us all how clever you are....