Liste des Groupes | Revenir à se design |
"Edward Rawde" <invalid@invalid.invalid> wrote in messageI can't see any crud. And comparing the FFT's of the outputs of U2 and
news:vf7c4h$1m5m$1@nnrp.usenet.blueworldhosting.com...But I suspect that component tolerances and mismatched FETs willCan anyone tell me what causes the following feature of the circuit
ruin it.
below? This circuit is not exactly the same as the previous one but
all versions seem to have this behaviour.
Run a simulation and view the output.
You can see that there's distortion until about 1.8 seconds when it
disappears. View J1 or J2 gate voltage. You can see that the crud
suddenly reduces at 1.8 seconds. What's causing that and is there a
way to make the circuit always run in reduced crud mode?
I'll be back in about a week to thank whoever can explain this.
Les messages affichés proviennent d'usenet.