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"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of real time. There are spots early in the process where it slows down, but not for long.Edward Rawde wrote:It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote desktop.Bill Sloman wrote:>This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the>
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
>
First I corrected the usual line wrap issues.
>
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
>
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
>
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth,
Bill's original LTSpice source worked for me "as is."
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds.
24.1.0 seems to be faster.
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