Re: 1kHz 130dB distortion sinewave oscillator.

On 2/02/2025 4:26 am, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnl3gl$30im$1@dont-email.me...

On 1/02/2025 4:37 pm, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...

On 1/02/2025 1:34 pm, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...

On 31/01/2025 5:47 am, Edward Rawde wrote:

Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.

But at least I know what mine are doing.
>

This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
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Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
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Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.

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This is a strange circuit.

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It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
>

One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
>
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the
source
or
drain.
>
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and
I'm
not interested enough to try and work how it is actually working.

>
I've modified the circuit to make sure that FET gate doesn't get forward-biased.

>
Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?
>

>
As John May pointed out a long time ago, the J113 isn't a great choice for the application.

>
Did he say why?
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   I've swapped in a J111. The integrator around U6

isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot
of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.

>
Sorry bill but I don't get why you would sabotage the circuit like that.

>
You aren't a quick study.
>

Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.

>
Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.

>
Perhaps if you measure the distortion only when the stabilisation circuit isn't feeding anything into the integrator wrapped
around U6.
>
The current feed to set the output level by balancing out  the inputs from the rectifiers was feeding in current when it should
have been sucking it out, so it wasn't a well thought-out design.
>
Here's a version of that circuit  which does work sensibly, even if the harmonic content of the output is only about 60DB below
the fundamental.

 But that's completely nuts Bill.

You don't seem to be able to follow the logic. In fact the 220k damping resistor at R4 was too with a 1uF integrating capacitor at C3 and reducing to 33k gave a very slightly under-damped response, and dropped the harmonis to about 75dB below the fundamental.

If I really do want 1kHz with -133dB harmonic distortion in reality then I'm prepared to wait 20 seconds for it.

But somebody actually using the circuit would want the distortion to be equally low at 40 seconds and later,

In fact I'm prepared to wait a minute or two if that's what it takes for the harmonic distortion to go down to -133dB.

But don't seem to appreciate the risk that it might start going up again.

If there's a problem with the design around U6 then why doesn't that also apply to U7 and U9?

They are acting as phase shifters, not integrators

It's not intended as a volume production design. I might make two or three boards and test it.
But I don't have equipment capable of measuring -133dB harmonic distortion.

Get a 20b-bit A/D converter chip that is faster enough for audio, damp a few second of it's output into a memory chip and run a Fourier transform   on that data.

I would also be prepared to make adjustments to the circuit for minimum distortion.
This circuit might have up to six adjustments if built for real so it can be adjusted for correct output level and minimum
distortion.
 The circuit included below might be my final offering on this matter.
There's nothing visible at 2kHz and 3kHz is barely visible.
It requires only a cheap quad op amp package in addition to the two LT1115 devices.
 If you can show me a circuit which has -133dB harmonic distortion and also faster settling time then I'd like to see it but if
you're going to insist that it has to have only -60 dB harmonic distortion performance (which interestingly is about that of your
own circuit) just because the settling time can be made shorter then I'm sorry but all that's going to do is make me wonder about
your mental health.

Wonder all you like. You psychoanalytic skills seem to be on par with your circuit design skills.

If you believe that a real version of the circuit below could not be adjusted to better than -130dB (with suitable test equipment)
then please let me know.

I don't have any strong opinion on the subject, but I wouldn't spend money to find out.

It might take an hour to complete the adjustments but that's ok with me because as previously stated it's not intended as a
production design which just works after assembly.

There are better approaches.

It takes my computer about 10 minutes (LTSpice 24.1.1) to complete 20 seconds of simulation for the following circuit.
I usually watch the output and the current in each of the four diodes.
 When it's done, take a sample of the output near 20s and FFT with Blackman-Harris window.

I'll pass.
--
Bill Sloman, Sydney