Sujet : Re: Cap C-V test
De : jrwalliker (at) *nospam* gmail.com (John R Walliker)
Groupes : sci.electronics.designDate : 04. May 2025, 15:11:26
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vv7sie$1epp4$1@dont-email.me>
References : 1 2 3
User-Agent : Mozilla Thunderbird
On 04/05/2025 03:17, john larkin wrote:
On Sun, 4 May 2025 02:11:47 +0200, Lasse Langwadt <llc@fonz.dk> wrote:
On 5/1/25 22:09, john larkin wrote:
>
https://www.dropbox.com/scl/fi/a7425c69k3w8wx8tqjpq5/X110_CV_Test.jpg?rlkey=pc3c0b12ncswv6ajrn148stdk&raw=1
>
>
The DUT is a Venkel 2.2 uF 100v 1812-size ceramic cap. I need to run
it at 48 volts. 0.8 uF is probably OK. I have room on my board so I
guess I'll add another cap in parallel.
>
or in series, I believe there are some automotive standards that call
for that on high current lines because ceramics tend to fail short with
mechanical stress
>
Two of those caps in series would make about half the capacitance of
two in parallel, but ESR and ESL would suffer by 4:1.
We don't see many ceramic cap failures. Our worst parts are "sealed"
relays that actually aren't. Some switches, too.
We don't use surface-mount film caps. They are awful.
Even the PPS type?
John
Cap C-V test
Re: Cap C-V test