Re: Predictive failures

john larkin wrote:

Don wrote:

Don Y wrote:

Is there a general rule of thumb for signalling the likelihood of
an "imminent" (for some value of "imminent") hardware failure?
>
I suspect most would involve *relative* changes that would be
suggestive of changing conditions in the components (and not
directly related to environmental influences).
>
So, perhaps, a good strategy is to just "watch" everything and
notice the sorts of changes you "typically" encounter in the hope
that something of greater magnitude would be a harbinger...

>
A singular speculative spitball - the capacitive marker:
>
   In-situ Prognostic Method of Power MOSFET Based on Miller Effect
>
   ... This paper presents a new in-situ prognosis method for
   MOSFET based on miller effect. According to the theory
   analysis, simulation and experiment results, the miller
   platform voltage is identified as a new degradation
   precursor ...
>
   (10.1109/PHM.2017.8079139)

>
Sounds like they are really measuring gate threshold, or gate transfer
curve, drift with time. That happens and is usually no big deal, in
moderation. Ions and charges drift around. We don't build opamp
front-ends from power mosfets.
>
This doesn't sound very useful for "in-situ" diagnostics.
>
GaN fets can have a lot of gate threshold and leakage change over time
too. Drive them hard and it doesn't matter.

Threshold voltage measurement is indeed one of two parameters. The
second parameter is Miller platform voltage measurement.
    The Miller plateau is directly related to the gate-drain
capacitance, Cgd. It's why "capacitive marker" appears in my
original followup.
    Long story short, the Miller Plateau length provides a metric
principle to measure Tj without a sensor. Some may find this useful.

Danke,

--
Don, KB7RPU, https://www.qsl.net/kb7rpu
There was a young lady named Bright Whose speed was far faster than light;
She set out one day In a relative way And returned on the previous night.