Re: Zilog stopping Z80 production

On 4/24/24 04:00, Don Y wrote:

On 4/23/2024 5:08 PM, Edward Rawde wrote:

It must be trivial to get a VHDL/Verilog model and make your own by now.

 
The problem with all the early/simple/trivial processors is getting
the rest of the system to run as fast as the core can.  E.g., running
a core at ~200MHz and expecting the same bus timing means < 5ns memory.
 
(for a Z80, that would be ~10ns as the bus timing is inherently slower)
 

>
how much memory can it address?
>