Re: configuring an Efinix T20

On 07/09/2024 16:58, john larkin wrote:

On Sat, 7 Sep 2024 15:19:59 +0100, John R Walliker
<jrwalliker@gmail.com> wrote:
 

On 06/09/2024 23:50, john larkin wrote:

>
I'm planning to use a Raspberry Pi RP2040 processor chip to configure
and then talk to an Efinix T20-FG256 FPGA.
>
Has anyone done this, or at least configured a T20 from a
microprocessor?
>
The RP2040 only has 30 GPIO pins, and many are dedicated to other
stuff, so we want to share a lot of things on one giant SPI bus,
including the FPGA config and then an SPI port on the FPGA to read and
write registers.
>
It looks like four of the T20 config pins need pullups. I wonder why
their guidelines show four separate resistors. Why not one resistor?
Why have resistors at all?
>
SS_N needs a pulldown. Why not ground it?
>
https://www.dropbox.com/scl/fi/x0gvvwqg42vhryu6610ve/Efinix_Config_1.jpg?rlkey=udy24brtumvdzfd2sp4l6yhwf&raw=1
>
>
It's always a moment to celebrate when a "config done" LED lights up.
>
I could easily get this wrong, so it would be great if I posted some
schematics and notes and someone could eyeball them for me.

>
If you need some more i/o pins, why not use the RP2350B?  They
definitely exist - I have one in front of me:
https://shop.pimoroni.com/products/pga2350?variant=42092629229651
>
John

 It only has two more package pins, as I recall. How many GPIOs?

No.  The RP2354B has 24 more package pins and 18 more GPIOs than
the RP2040.
Its an 80-pin package with 48 GPIOs.

It's new and a bit buggy and not widely available, so we'll stick with
the 2040. The only upsides are the higher clock rate and the faster
floats, which aren't critical in the product line that we are
developing now.

Yes, there are some bugs.  The most critical is probably the one
relating to on-chip pull-downs, but it can be solved with external
resistors.  The ADC is improved.  There are more and better
i/o state machines.  There is a lot more on-chip RAM and there
will soon be the option of flash in the same package.
There may not be production quantities of the RP2354B readily
available yet, but there are certainly some around for prototypes.
As I mentioned, I have one.

 Why didn't they make it pin compatible, drop-in to the 2040? Why not
put in a mac/phy instead of the extra CPU cores?

That would have been nice.  However, I don't think the RISC-V added
any chip area as the design appears to be i/o bound.

 Using one SPI bus for multiple loads will save pins. We should be able
to configure the FPGA and then read/write registers with a shared SPI
interface, and hit some other things too.
 It might be tricky to share the interface to the WizNet ethernet chip,
and sharing the flash interface wires is something we don't want to
even think about.
 Of course, once I have an FPGA, I'll have a zillion port pins
available.