Sujet : Re: port pins
De : dan (at) *nospam* djph.net (Dan Purgert)
Groupes : sci.electronics.designDate : 12. Sep 2024, 21:05:24
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <slrnve6ic4.c2t.dan@djph.net>
References : 1
User-Agent : slrn/1.0.3 (Linux)
On 2024-09-10, john larkin wrote:
Something I've wondered about:
>
Suppose we have a c program running on some little uP, and it has some
integer variable value, 8 or 12 bits or something, and wants to drive
a parallel DAC off-chip.
>
The msb...lsb bits of the variable obviously have to get to the right
pins of the DAC.
>
So, in general, how does one pick the physical i/o port pins on the
uP, to get the order right? The PCB layout is easiest if we just wire
the DAC to the handiest port pins.
I pick whichever I/O port is
- free
- close
- not an absolute pain layout wise.
On the PDIP-28 ATMegaX8's; this usually amounts to PortD, down the
left-hand side (assume Pin1 is upper-left). There's only VCC/GND to
contend with in the middle (7,8) and then potentially the oscillator on
PB7,0 (9,10).
If I'm using the internal oscillator, PortB is also viable (but it gets
a bit weird, since the layout is 6,7,0,1,2,3,4,5 (pins 9,10,14-19))
>
One could test and bit-bang each bit and port individually, and then
strobe the DAC, but that's inelegant.
Ow, yeah, that'd be painful.
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