Sujet : Re: DRAM accommodations
De : bill.sloman (at) *nospam* ieee.org (Bill Sloman)
Groupes : sci.electronics.designDate : 17. Sep 2024, 15:04:09
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vcc28s$3hn5f$1@dont-email.me>
References : 1 2
User-Agent : Mozilla Thunderbird
On 17/09/2024 11:47 pm, Chris Jones wrote:
On 6/09/2024 8:54 am, Don Y wrote:
Given the high rate of memory errors in DRAM, what steps
are folks taking to mitigate the effects of these?
>
Or, is ignorance truly bliss? <frown>
>
Do we know whether DRAM chips implement ECC internally? It seems an obvious thing for them to do. Of course it wouldn't help with bad solder joints on the DIMM, but it would help with many kinds of faults on the chip.
It seems unlikely. The only ECC coding that I got close enough to plan to implement used a 72-bit word to protect 64-bits of the word content.
I suppose there might be serial access DRAM chips that would spit out 64-bit words, and they could offer ECC protection inside the chip by adding the 8-bit checksum when the data went in, and using it to correct the output whenever the data was read out.
-- Bill Sloman, Sydney
DRAM accommodations
Re: DRAM accommodations
