Re: faster DDS clock

On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@650pot.com> wrote:

Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
 
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
 
 

>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
>
Any asymmetry in the square wave turns into subharmonic jitter.
>
A 2:1 PLL would probably get my vote.
>
Cheers
>
Phil Hobbs

I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.