Re: faster DDS clock

On Wed, 18 Sep 2024 21:58:13 -0000 (UTC), piglet
<erichpwagner@hotmail.com> wrote:

john larkin <jl@650pot.com> wrote:

Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
 
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
 
 

>
How important is it that the duty cycle is 50%?

Not super critical. The product is an arbitrary waveform generator and
a small wobble in the output sample timing won't be noticed.

I'm thinking I can keep the duty cycle close to 50%.

The falling-edge jitter should be about the same as the rising edge
jitter.

A dual DAC would save me a lot of data lines, so maybe I can go from
single-8 to a dual-10 DAC or something.