Re: faster DDS clock

On Thu, 19 Sep 2024 21:49:30 +1000, Chris Jones
<lugnut808@spam.yahoo.com> wrote:

On 19/09/2024 7:39 am, john larkin wrote:

Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
 
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
 

>
Doing that doubling trick when you take a sine wave oscillator and feed
it via a comparator to the reference input of a PLL has a subtle
advantage: Any additive 1/f voltage noise affecting the input stage of
the comparator, or from any buffering stages for the sine wave before it
gets to the comparator, will move the rising and falling edges of the
comparator in opposite directions, and if both the rising and falling
edges are clocking the phase detector of the PLL then the 1/f noise will
cancel out at low frequencies and not make it through the loop filter,
and not cause phase modulation of the RF output from the PLL. It's
really a nice bonus. I guess it wouldn't work so well if the incoming
waveform had asymmetric slew rates.

I can't feed my DDS into a PLL; frequency change has to be
instantaneous, and cover a huge frequency range.

I'm generating waveforms that simulate a geared jet engine, which is a
noisy shakey vibrating thing, so nanoseconds of jitter/phase noise
doesn't matter much.

Using a synthesizer would be great, like an LMX2571... no filters or
comparators needed.  $7 and we'd be all done. But it takes way too
much math to program.