RE: Advice for active FPGA forums

On 11/10/2024 23:02, JM wrote:

On Fri, 11 Oct 2024 21:57:16 +0100, Mike Perkins <spam@spam.invalid> wrote:
 

I am currently using an Intel Cyclone V, a 5CEBA2F23C8N and a LPDDR2 memory.
>
The reason for this initial choice is due to a Terasic development board
that used a Altera/Intel high end Cyclone V device with a functioning
LPDDR2 IP. Some code was breadboarded here.
>
Unfortunately I can't get the LPDDR2 IP to work on my PCB. I get errors
and I have given up.
>
So I have made my own interface. This 'can' function fine without error,
but as the design has become more complex I now struggle for the memory
to function at 225MHz clock speed, being the minimum speed I need for a
32bit DDR2 memory. I can select clock phase for the internal clock,
memory clock and DQS strobes.
>
I'm struggling with setting clock speed and appropriate timing where the
timing simply fails, despite setting the options to max speed. The
delays are simply too many ns.
>
In short I am throwing in the towel with a view to reconsidering
alternative architectures and FPGAs. I should be able to reuse most of
my code.
>
I was wondering if anyone could recommend a generic type of forum that
could assist with feedback. Yes I know there are AMD and Intel FPGA
sites but they are very specific to those makes.
>
There is comp.arch.fpga but that's pretty much defunct.
>
Any suggestions?

 Post on eevblog, showing your PCB layout.

Timing analyzer suggests much of the problems are in the delays within the FPGA. I can make the LPDDR2 interface work, but with a lower content in the device, where routing delays seem to be excessive. At 225MHz memory clock speed this is well below the limit of 533MHz. I have considered trace impedance with the consequence of double clocking etc but will double check this.
Currently I only have a narrow sweet spot at 150MHz.
--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk