RE: Advice for active FPGA forums

On 11/10/2024 23:07, Theo wrote:

Mike Perkins <spam@spam.invalid> wrote:

I am currently using an Intel Cyclone V, a 5CEBA2F23C8N and a LPDDR2 memory.
>
The reason for this initial choice is due to a Terasic development board
that used a Altera/Intel high end Cyclone V device with a functioning
LPDDR2 IP. Some code was breadboarded here.
>
Unfortunately I can't get the LPDDR2 IP to work on my PCB. I get errors
and I have given up.

 Argh, I hate doing stuff with DDR on FPGAs.  It seems the failure modes (on
Intel anyway) are just 'it doesn't work' with no feedback as to why.  I end
up randomly tweaking things and rebuilding in the hope that something will
work one day.

That has become my conclusion too. The LPDDR2 IP is also a little dated and no longer shipped with later versions of Quartus. That does concern me too as to why this might be the case?

Usually there's a bunch of board-level timing parameters (in picoseconds) in
the IP config, which they expect you to work out from simulating your board
in HyperLynx or similar.  How did you generate those parameters, or did you
just copy the ones from the dev board?

That's a good point, I used those from the dev board.

It's worth looking at the Intel/Altera 'Development Kit' boards (for example
'Cyclone V SX SoC Development Kit' as the PCB layout may be available -
worst case you could steal the DDR routing and thus the timings.  The
Terasic boards are their own product and the layout isn't available.

I have used the Terasic development board that does have a LPDDR2 memory IC.

(although LPDDR2 is a bit less common so there may not be one for that)
 

So I have made my own interface. This 'can' function fine without error,
but as the design has become more complex I now struggle for the memory
to function at 225MHz clock speed, being the minimum speed I need for a
32bit DDR2 memory. I can select clock phase for the internal clock,
memory clock and DQS strobes.
>
I'm struggling with setting clock speed and appropriate timing where the
timing simply fails, despite setting the options to max speed. The
delays are simply too many ns.

 It may be the part is just not fast enough to do that in soft logic - the
last FPGA I used with a soft DDR controller was the Stratix 4, and I think
that still had some hard parts.  It's a quite low end part.

The part is quoted with a clock speed of 400 MHz and I get a narrow sweet spot at 150 MHz. The soft logic is letting the interface down.

I don't remember the specifics of what's on the Cyclone V E, but I'd try to
get the hard IP to work.  I've only used DDR3 with them, though, so can't
speak for the LPDDR2 controller.
 

In short I am throwing in the towel with a view to reconsidering
alternative architectures and FPGAs. I should be able to reuse most of
my code.
>
I was wondering if anyone could recommend a generic type of forum that
could assist with feedback. Yes I know there are AMD and Intel FPGA
sites but they are very specific to those makes.
>
There is comp.arch.fpga but that's pretty much defunct.

 It's not defunct, it's resting :-)  Nobody is posting there but it doesn't
mean people aren't reading it if somebody does post something.
 Otherwise:
 eevblog.com -  not sure what the FPGA section on the forum is like, but it
has traffic
 edaboard.com - this used to come up in searches a lot, but ~10 years ago it
seemed to be mostly filled with Indian students asking about their
coursework.  I don't know if it's better these days.
 The Altera forum used to be good, but Intel made a complete mess of it when
they took it over, and it's now just a PITA.
 I'm not sure what the Xilinx/AMD forum is like these days.
  Although TBH your problem is pretty niche, so the number of people who have
done what you're trying to do is likely to be very small, and the chances of
them being on a forum and seeing your post may be limited.
 Theo

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk