Re: High purity 1kHz oscillator

On Tue, 22 Oct 2024 12:53:06 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf7c4h$1m5m$1@nnrp.usenet.blueworldhosting.com...

But I suspect that component tolerances and mismatched FETs will ruin it.

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Can anyone tell me what causes the following feature of the circuit below?
This circuit is not exactly the same as the previous one but all versions seem to have this behaviour.
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Run a simulation and view the output.
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You can see that there's distortion until about 1.8 seconds when it disappears.
View J1 or J2 gate voltage.
You can see that the crud suddenly reduces at 1.8 seconds.
What's causing that and is there a way to make the circuit always run in reduced crud mode?
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I'll be back in about a week to thank whoever can explain this.

If this was a real lab with real hardware and test equipment,
I'd need to see your test settup, because that's usually the
reason you get 'strange' test results.

1.5sec and 2sec plots both 'look' the same here - full of
crud.

Different crud, depending on whether .jpg or bmp formats . . . ;-]

RL