Re: 38 Mb/mm^2 SRAM

On 10/31/24 21:47, Phil Hobbs wrote:

Jeroen Belleman <jeroen@nospam.please> wrote:

On 10/31/24 20:42, Joe Gwinn wrote:

On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
<jeroen@nospam.please> wrote:
>

On 10/31/24 16:01, Sylvia Else wrote:

On 31-Oct-24 8:46 pm, Jan Panteltje wrote:

SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
major improvements
>
https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main
>
gate all around tech...
   38 Mb/mm^2
>

If my arithmetic is right, there are about 50 atoms of silicon per cubic
nanometre. Surely we're approaching the limits of this.
>
Sylvia.

>
The stated '2nm process' has little to do with the actual size
of features on the chip. It has become a sales argument rather
than the true size of something.

>
If I recall, it actually has a fairly precise definition, that it's
the smallest feature size that can be manufactured.  So, it's roughly
equivalent to a pixel, and it takes many pixels to make a legible
letter or number.
>
Joe Gwinn

>
It used to, to be sure, but no more. You can't image 2nm details
with 13nm EUV.
>
Jeroen Belleman
>

 You can, actually, because of the high contrast of photoresist. You do have
to use multiple patterning steps per level.
 Cheers
 Phil Hobbs
 

To some extent, yes, OK.
Talking of photoresists, these are usually polymers, that is, large
molecules. At some point, that will also set a limit on the minimum
size of features.
Jeroen Belleman