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On Sun, 3 Nov 2024 20:53:19 +1100, Bill Sloman <bill.sloman@ieee.org><snip>
wrote:
On 3/11/2024 7:56 pm, Cursitor Doom wrote:On Sun, 3 Nov 2024 13:27:26 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
>On 3/11/2024 6:21 am, Cursitor Doom wrote:On Sat, 2 Nov 2024 13:07:32 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
>"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vg4fff$3lok1$1@dont-email.me...On 2/11/2024 12:01 pm, Edward Rawde wrote:"Cursitor Doom" <cd999666@notformail.com> wrote in message news:vg3575$3bio0$1@dont-email.me...
Edward Rawde wasn't asking how to stabilise the voltage difference. He was asking how to display the small short term variations in voltages on the screen in the presence of a large voltage difference - the P-channel and N-channel FETs in question were operating with their gates a couple of volts above and below ground respectively and he wanted to see the mV difference in gate voltages through a single cycle of the sine wave.The fact is that a 1fF cap would have had the desired effect without>>>Is there an easy way to remove a DC offset from a simulation trace so that my n and p gate signals can be superimposed after
startup?
There is but Cursitor Doom doesn't know it.
Yeah, still haven't heard of capacitors.
Non sequitur. The simulation program involved - LTSpice - does
accommodate capacitors, but you don't need to add them to the circuit
being simulated to do what Edward Rawde was asking for.
compromising the circuit's performance. Why do you feel the need to
complicate everything? Oh yes, to show us all how clever you are....
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