Re: Final final 1kHz oscillator

"Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...

On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
>

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...

On 9/11/2024 7:39 pm, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...

On 9/11/2024 7:43 am, Edward Rawde wrote:

This is the simplest circuit I can come up with.
Harmonics are more than 80dB down in simulation.
FFT the last 30 seconds.
There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
on exactly how much output is selected for the FFT. You may see different results.
>

>
I have fixed my circuit but it raises more questions than it answers.
This circuit deliberately has no text and no u symbols so should be ready to simulate.
If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
standing in the way of 90dB.
Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

>
Spectral purity might be fine for all I can tell but the output
amplitude is all over the place, even if the sim is left to run its
full course.

In that case there is some unknown difference between your simulation and mine.
I just copy/pasted it directly from my post into sine.asc and ran the simulation.
The output is totally stable after 20 seconds and remains stable for the rest of the simulation.

One of the reasons this circuit can produce such a pure output is the filter components R12 and C6.
This makes it so that what is sent to the FET gate can't be much different from DC when the amplitude control loop is locked on to
the correct control point.

But the filter components introduce a lot of lag (Bill also pointed this out).
So I tried another op amp as a lag compensator (which also inverted so I change to a P FET).
This worked fine and the output was almost immediately stable at the correct level.
But it also had the effect of introducing noise to the extent that I couldn't get below 50dB down.

So I looked for another solution.
One way to force the amplitude control loop to lock is to do just that.
Make it so that the control voltage can't go too far outside the required range.
That's what the diode clamp does.

Is your version of LTSpice fully up to date both main program and library?
If so then it wouldn't surprise me if differences between computers cause differences in simulation of this circuit.
Try adjusting the last two digits of the value of R9

Also, what's the purpose of the 6 diodes in series at the
top of the schematic? If you need to drop 4V there ought to be a more
elegant way of doing it!
>
>
>

There are two things I don't understand about my own circuit.
>
1. Why does LT1678 work fine in position U2 but LT1057 does not.
2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?
>
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