Re: DDS follies

On Sun, 1 Dec 2024 12:34:31 -0800, dplatt@coop.radagast.org (Dave
Platt) wrote:

In article <fmknkjpda1s2nc6d67nlqhf559v5j558ks@4ax.com>,
john larkin  <JL@gct.com> wrote:
>

I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down.

>
I tried doing some waveform generation by something like this method
in an ICE40 FPGA, creating a 10.7 MHz IF signal for an FM-stereo
alignment generator.  As I recall I used three output pins,
and a very simple resistor DAC.
>
The result was a nasty-looking waveform, with some serious switching
glitches at some transitions between values.  There was enough
difference in signal-propagation time between the pins and the
driving gates to cause some race conditions, leading to a short
high-value spike during the transition.
>
Even putting the pins into registered-output mode didn't help very
much... the register-being-clocked-to-pin-transition delays weren't
constant.  I think I was just asking a low-end FPGA to do things
it wasn't really designed to do.
>
It would have taken multiple filter stages to get rid of this.
Using Schmitt comparators (such as you suggest) would have
gotten rid of the glitches (assuming that board and part
parasitics didn't let them bleed through) but then I'd have
had to low-pass filter the comparator output again to get
something like a sinewave.
>
One possible way around this problem would be to arrange the outputs
to operate as a Gray code (or similar), so that one can guarantee only
a single pin transition per clock.  I imagine there's probably an
R-type DAC topology which could support this, but I haven't worked
with one personally.
>

We use home-made 1-bit delta-sigma DACs sometimes. Just an RC out of
an FPGA pin. That's good for slow stuff like an offset trim or tuning
a VCXO or whatever. It's a bit better than PWM but it's still crazy
slow.

I'm guessing that a 1-bit DDS,  just filtering the MSB of the sine
lookup table, would be awful too. But imagine a 65K x 1 bit sine
lookup!

Hmmm, that makes a square wave: Out = In. Never mind. [1]

I trekked down the hill to retrieve my DDS book and my treasured
"Signals and Systems for Dummies" paperback. So I can snoop a little
theory now.

I might simulate some cases, filter and all, but LT Spice is
impressively klutzy at digital stuff.

Here's a past attempt. Instead of drawing a zillion flops and gates, I
faked an analog phase accumulator.

https://www.dropbox.com/scl/fi/8pilwsykjo9bngqarzx0j/JLDDS_100M_4K.jpg?rlkey=dgtrlxdz4zvc22z297prc5rxk&raw=1

I think some of my kids can do Matlab or whatever.



[1] but might such a lookup table generate delta-sigma?

[2] Does it ever make sense to sum two triangles?