Re: DDS follies

On 12/1/24 04:43, john larkin wrote:

We have an old product, a 4-channel arb, that specifically simulates
pickups from complex rotating machines, namely jet engines.
 https://highlandtechnology.com/Product/V375
 It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set
registers and I'm clocking at 40 MHz, max out 15 MHz.
 The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
 I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
jocks have suggestions.
 We do need the *exact* same settability as the ADI part, and it's
critical that, if we set several frequencies at some multiple of the
lowest one, the frequencies are exact and the phase relationships
never change; gears don't change their teeth or slip.
 Jitter isn't too big a deal; we are simulating machines.
 I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down. The max final
frequency could be maybe 20 or 25 MHz, somewhat higher than the old
system could do.
 Any thoughts or dirty tricks? I'll brainstorm this with my
signals-and-systems jocks, but want to think about it first so I don't
look too silly.
 

afaict the AD9830 is just a phase accumulator and a lookup table, you should be able to do that quite a bit faster than 40MHz in an FPGA
It might be possible to use some deserialiser DDR trickery to place
edges between the main clock edges