Re: DDS, again

On Wed, 11 Dec 2024 10:02:13 +0100, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 12/11/24 03:38, john larkin wrote:

I have been unsuccessful in getting LT Spice to simulate a DDS
frequency generator. It's bad enough trying to make the NCO part, but
whenever I get close it stalls or throws convergence errors.
 
So I wrote a PowerBasic program that's the 32-bit NCO...  GC_Num.exe.
 
Making a proper .WAV file would be a nightmare, so it outputs as a
text file with just    time  data    per line, where  data  is the
selected number of MS bits of the phase accumulator.
 
LT Spice can read the file, and then do whatever it wants: sine, DAC,
filter, comparator, FFTs.
 
https://www.dropbox.com/scl/fo/o0mdxxqvxupg6ynz7i7rx/AMPMbv9NOY4mJFXggTGUqJ8?rlkey=9ecl38npbgy8kxuzd9bako4kr&dl=0
 
Spice reads the file as a piecewise-linear thing, so wrecks the nice
MSB data steps. I had to fool it by outputting each clocked phase
accumulator value twice, as
 
bits   time
bits   time+0.9*clock_period
 
same data bits both lines. Looks pretty steppy.
 

>
On Linux, we have 'sox' that can convert between time-value
pairs and .wav in either direction. I suppose there must be
a Windows version. I suspect the piecewise-linear problem
will still be there.
>
As for the convergence problems: LTspice doesn't like
discontinuities. Jim Thompson approximated everything with
smooth functions. His favourite was tanh.
>
Jeroen Belleman

LT will input a binary .wav file without the piecewise thing, I think,
but I didn't want to add the conversion step. Or learn yet another
program. And I sure didn't want to write the PowerBasic code to make a
.wav file.

The irony is that after some nontrivial amount of coding, I think I'll
just use the MSB of my 40 MHz 32-bit phase accumulator as our waveform
clock. Nobody important will notice the jitter.

The "RF" mindset, that one has to do the sine and dac and hi-rent
lowpass filter and comparator, is not only a bunch of work and
expense, it gets really nasty at low frequencies.

Oh well, the project was educational and will probably be useful some
other day, when clock purity matters more.

It would be interesting to try to stay all on-chip in the FPGA, to
digitally filter the MSBs of my 40 MHz NCO with some digital filter
running on a faster clock.

My guys say that they could run the phase accumulator at at least 100
MHz in an Efinix FPGA, and that offers ideas too.

Tanh is indeed slick. I have some logical statements in my LT Spice
NCO that it may not like.