Re: An LTSpice test bed for the gain control FET in "low distortion" oscillators

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Sujet : Re: An LTSpice test bed for the gain control FET in "low distortion" oscillators
De : bill.sloman (at) *nospam* ieee.org (Bill Sloman)
Groupes : sci.electronics.design
Date : 22. Dec 2024, 07:18:02
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Message-ID : <vk8aur$gbls$1@dont-email.me>
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On 22/12/2024 1:39 am, Bill Sloman wrote:
The Jim Williams low distortion Wein bridge depends on a FET for amplitude control, but the FET isn't the perFectly linear resistor we'd like it to be.
 And minimising the rectifier ripple in the gain control voltage applied to the gate of the FET is tricky.The test bed example below is set to apply 10uV of 2kHz ripple, which is less than any of my circuits can manage - 2mV is closer to what the circuit I've posted could manage.
 I've put together a little LTSpice test bed to try to get some idea of how non-linear the FET channel is.
>
It looks as if there about 70uV of higher harmonic content in the 10.4mV peak to peak voltage across the FET for the 1V peak to peak 1kHz test signal.
Tinkering got that down a bit to about 18uV with 3.5mV of 2kHz ripple - that seems to be the sweet spot where the 2kHz and 3kHz harmonics are both about 60dB below the 1kHz fundamental - moving away from that pushes one up and the other down.
What's going on in the FET is still a mystery to me. I'd have to dig into the FET Spice model to get any idea. The semi-conductor physics should be well understood - I've got a textbook on my bookshelf that claims to spell it out - but translating that into a hand-on feel for what's actually going on isn't something I've ever needed to do.
--
Bill Sloman, Sydney

Date Sujet#  Auteur
21 Dec 24 * An LTSpice test bed for the gain control FET in "low distortion" oscillators2Bill Sloman
22 Dec 24 `- Re: An LTSpice test bed for the gain control FET in "low distortion" oscillators1Bill Sloman

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