Re: Current mirror version of the lowish distortion 1kHz sine wave osillator

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmlpii$364is$7@dont-email.me...

On 15/01/2025 11:33 pm, Bill Sloman wrote:

This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
>
R30 isn't a real part - it's just there to let me do an FFT on the correction signal.
>
The circuit just copes with worst case capacitors - 15.15nF and 14.85nF - at C5 and C6, as it was intended to do. Using a trim
pot to take out component tolerances would let you get away with a smaller correction signal injecting smaller doses of the odd
harmonics.
>
The circuit does cry out for monolithic dual transisors.The On-Semi
NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.

>
There was a dumb error in the original circuit. The two transistor switch (Q5 and Q6 in the original circuit) that turned the full
wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working as
intended after it had settled down, but it made start-up a bit tricky.
>
Here's the corrected version. It's performance isn't noticeably differ
>

Fix obvious line wraps.
Search for Elektronik and fix remaining line wraps.
Move U1 down to connected position and connect + supply.
Save File.
Attempt to start simulation but get "Duplicate Q5" message.
Remove Q5 and copy Q10 (it's now Q4).
Save file.
Start simulation and click on Vout.
Note simulation speed about 20us/s (core i7 SSD).
Stop simulation.
Move file to other remote desktopable computer running LTSpice 24.1.0
Open schematic
Attempt to run simulation but get strange errors, one for each of U1 - U10
Attempt to copy one of the errors but get unhelpful right click menu.
Open log directly from file system to get exampe of error message:
This sub-circuit name is not defined. X�U1 N040 N032 N005 N050 N039 LT1360
Use previous experience to fix errors in seconds (rather than hours) by editing schematic file to remove .ENDS from BAS70 line.
Start simulation and click on Vout.
Note simulation speed of about 25us/s
Leave simulation running but expect it to run out of disk space.
Go back to other work on main computer.