Re: 1kHz 130dB distortion sinewave oscillator.

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnka4g$3ut8i$1@dont-email.me...

On 1/02/2025 1:34 pm, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vnim5i$3hnrj$1@dont-email.me...

On 31/01/2025 5:47 am, Edward Rawde wrote:

Approaching 130dB now. Any suggestions for improvement?
It wouldn't be hard to add another four rectifier phases but then I'd have more components than Bill.

But at least I know what mine are doing.
>

This circuit was simulated in LTSpice 24.1.1 with all component updates as of 30th January 2025.
>
Take a sample near 20s and FFT on current zoom extent with Blackman-Harris window.
It's approaching 130dB at 2kHz and approaching 140dB everywhere else.
>
I do not know why C13/R28 and similar are needed but without them the simulation speed goes down to us/s
It appears that LT1115 doesn't like being simulated with very little load on its output.
Whether or not that's true in reality I've no idea and it may not be the case in earlier versions of LTSpice.
>
Simulation speed in 24.1.1 appears to be about twice as fast as earlier versions for this circuit.

>
This is a strange circuit.

>
It's also way more complex than it need be. Please see my most recent post.
I think you'll find the FET is operating conventionally. Roughly at the centre of its range when I last checked.
>

One problem with using an N-channel junction fet like J113 is that if you bias the gate at a higher voltage than the source or
drain, it acts as a diode and feeds current into the channel.
>
I've downloaded and run the second version of the simulation, and the gate doesn't seem to end up more negative than the source
or
drain.
>
It takes quite a lot of simulation time before the circuit starts acting as if were an amplitude controlled oscillator, and I'm
not interested enough to try and work how it is actually working.

>
I've modified the circuit to make sure that FET gate doesn't get forward-biased.

Why does it matter if the FET gate is forward biased during the first 10ms Bill?
That isn't going to make the FET explode is it?

>
As John May pointed out a long time ago, the J113 isn't a great choice for the application.

Did he say why?

 I've swapped in a J111. The integrator around U6

isn't well designed, and I've deleted a redundant resistor and added a huge damping resistor (R4). It means that there's a lot of
1kHz ripple on the gate voltage, and loads of harmonic content on the output - 2kHz is only 25dB below the fundamental.

Sorry bill but I don't get why you would sabotage the circuit like that.

Getting a low ripple rectified output to feed into the integrator isn't a trivial task. It's part of a negative feedback control
problem which you seem to be reluctant to recognise.

Please see the most recent circuit I posted.
It doesn't bother with DC stabilization circuits but it does do 133dB down on harmonics with pretty much nothing at 2kHz at all.

>
Bill Sloman, Sydney
>
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SYMATTR InstName R4
SYMATTR Value 6800k
TEXT -408 -744 Left 2 !.tran 0 20 0 1u uic
TEXT -416 -816 Left 2 !.options plotwinsize=0 numdgt=7 method=trap
TEXT -424 -648 Left 2 ;1kHz low distortion sinewave oscillator.
TEXT -424 -616 Left 2 ;Approaching 130dB. Edward Rawde 30 Jan 2025.
TEXT 1352 -640 Left 2 ;As modifed by Bill Sloman 1 Feb 2025, greatly degrading the distortion performance, but fixing some
start-up problems.