Re: SPLD output current protection

bitrex <user@example.net> wrote:

On 2/10/2025 6:07 PM, piglet wrote:

bitrex <user@example.net> wrote:

I have an SPLD with about 8 terminals exposed to the user I'd like to
protect against over current. They're very low-speed outputs (10s of Hz
at most), don't really want to spend a bunch for a chip like the L6374
as an intermediary, or the board space for a bunch of transistors to
discrete limit...
 
The SPLD has a max per-chip-side Vdd input current of 45 mA at 85 C TJ
and 22 mA at 110 TJ, and can sink 86 mA to ground per side, 41 at 110 TJ.
 
The outputs are configured as push-pull or open drain, depending on the
firmware/application, either way they can source or sink 40mA in
isolation. But no more than two outputs per side at a time will be in a
state such that they can sink/source current either way.
 
The uP I'm using has a very nice 10 bit differential ADC (9 bits if used
in bipolar mode) I'm thinking about just rigging it to two 4051s to
"scan" a current sense in each output line to implement the overcurrent,
can set different thresholds based on whether it's configured push-pull
or OD, but what might conservative limits be? And what rate to scan?
 
The SPLD is acting as a simple power supervisor and has a PWR GOOD line
to bring up the uP. In turn it gets a clock from the uP, I can set up
the SPLD to set all those outputs hi-z if it ever loses the clock (i.e.
uP hangs) as an extra layer of protection..
 

 
 
Ptc thermistor or polyfuse?
 

I'd rather use something KISS and actively monitor as a backup for sure,
but I haven't used those devices on low current output lines before, do
you have a suggestion for a suitable part? Thanks
 
 

I was thinking of something like the Murata PRG18 series?

But instead of one PTC per output maybe the mcu can monitor current in the
spld supply and ground pins. May need some amplification to keep sense
shunt resistance values low.


--
piglet