Sujet : Re: DDS question: why sine lookup?
De : bill.sloman (at) *nospam* ieee.org (Bill Sloman)
Groupes : sci.electronics.design comp.dspDate : 09. May 2025, 06:52:32
Autres entêtes
Organisation : A noiseless patient Spider
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References : 1 2 3 4 5 6 7 8 9 10
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On 9/05/2025 8:28 am, Phil Hobbs wrote:
john larkin <jl@glen--canyon.com> wrote:
On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
>
On 2025-05-08 14:58, john larkin wrote:
On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
>
On 2025-05-07 22:21, john larkin wrote:
On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:
>
On 5/7/2025 4:01 PM, john larkin wrote:
On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
<'''newspam'''@nonad.co.uk> wrote:
>
On 06/05/2025 16:48, john larkin wrote:
If the output frequency is known in advance, all ought to be
straightforward—pick a clock frequency that’s an integer multiple.
One VCXO-based PLL should be able to make that.
You can't pull a VCXO all that far
https://www.analog.com/en/resources/technical-articles/using-a-vcxo-voltagecontrolled-crystal-oscillator-as-a-clock-clk-generator.htmlsays in the range +/-100ppm to +/-200ppm. That implies having a VCXO clock running about 10,000 times faster than the output frequency you are trying to generate.
There's going to be a tolerance on the VCXO centre frequency as well. which isn't gong to help.
There's a reason why Direct Digital Synthesis is popular - it does finesse a lot of awkward problems.
-- Bill Sloman, Sydney
DDS question: why sine lookup?
Re: DDS question: why sine lookup?
