Re: LTSpice model for a SiC MOSFET

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Sujet : Re: LTSpice model for a SiC MOSFET
De : liz (at) *nospam* poppyrecords.invalid.invalid (Liz Tuddenham)
Groupes : sci.electronics.design
Date : 20. May 2025, 10:58:08
Autres entêtes
Organisation : Poppy Records
Message-ID : <1rcmono.1mb9yv615fdzkgN%liz@poppyrecords.invalid.invalid>
References : 1 2 3
User-Agent : MacSOUP/2.4.6
Bill Sloman <bill.sloman@ieee.org> wrote:

[...]
Capacitive divider using a spare core in the
mains supply lead as one plate of the capacitor?  (Depending on supply
frequency and required output current.)
 
I can't see how that could work.

If you used a three-core mains lead with one of the cores connected to
Neutral at the plug, one to Live at the plug and one floating, the
floating lead would take up a potential somewhere between the other two,
the stray capacitances between the leads acting as a capacitive divider.

The Live and Neutral leads are left unconnected at the equipment end and
the floating lead is connected to a rectifier system which takes it's
earth reference from the equipment being supplied.  It would be
approximately a constant-current supply, so a capacitor and zener diode
would be sufficient to stabilise it at the required low voltage.

The mains lead is acting as a high voltage capacitor but is a lot
cheaper and more reliable.

If you need a solid earth on the output, use a four-core cable.


--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

Date Sujet#  Auteur
18 May09:11 * LTSpice model for a SiC MOSFET88Bill Sloman
18 May15:15 +* Re: LTSpice model for a SiC MOSFET50john larkin
19 May03:23 i`* Re: LTSpice model for a SiC MOSFET49Bill Sloman
19 May04:38 i +* Re: LTSpice model for a SiC MOSFET34john larkin
19 May09:19 i i`* Re: LTSpice model for a SiC MOSFET33Bill Sloman
19 May14:29 i i +* Re: LTSpice model for a SiC MOSFET16john larkin
19 May18:02 i i i`* Re: LTSpice model for a SiC MOSFET15Bill Sloman
19 May19:28 i i i `* Re: LTSpice model for a SiC MOSFET14Edward Rawde
19 May23:14 i i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May08:23 i i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May08:26 i i i  `* Re: LTSpice model for a SiC MOSFET11Bill Sloman
20 May16:04 i i i   `* Re: LTSpice model for a SiC MOSFET10Mike Perkins
20 May17:38 i i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May18:03 i i i     `* Re: LTSpice model for a SiC MOSFET [OT]8Liz Tuddenham
21 May12:59 i i i      `* Re: LTSpice model for a SiC MOSFET [OT]7legg
21 May13:03 i i i       +* Re: LTSpice model for a SiC MOSFET [OT]5Liz Tuddenham
21 May18:16 i i i       i`* Re: LTSpice model for a SiC MOSFET [OT]4john larkin
21 May18:51 i i i       i +* Re: LTSpice model for a SiC MOSFET [OT]2Phil Hobbs
21 May19:19 i i i       i i`- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
21 May21:14 i i i       i `- Re: LTSpice model for a SiC MOSFET [OT]1Liz Tuddenham
21 May13:34 i i i       `- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
19 May19:26 i i `* Re: LTSpice model for a SiC MOSFET16Edward Rawde
19 May23:24 i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May08:43 i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May08:34 i i  `* Re: LTSpice model for a SiC MOSFET13Bill Sloman
20 May14:38 i i   `* Re: LTSpice model for a SiC MOSFET12Edward Rawde
20 May14:51 i i    +- Re: LTSpice model for a SiC MOSFET1john larkin
20 May14:54 i i    +- Re: LTSpice model for a SiC MOSFET1John R Walliker
20 May17:48 i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May18:44 i i     `* Re: LTSpice model for a SiC MOSFET8Edward Rawde
21 May07:39 i i      `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May14:42 i i       `* Re: LTSpice model for a SiC MOSFET6Edward Rawde
21 May16:26 i i        +- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May16:37 i i        `* Re: LTSpice model for a SiC MOSFET4john larkin
21 May16:43 i i         +* Re: LTSpice model for a SiC MOSFET2Edward Rawde
21 May18:52 i i         i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May18:49 i i         `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May14:33 i `* Re: LTSpice model for a SiC MOSFET14legg
19 May18:21 i  +* Re: LTSpice model for a SiC MOSFET11Bill Sloman
19 May20:48 i  i`* Re: LTSpice model for a SiC MOSFET10legg
20 May08:49 i  i `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May15:53 i  i  `* Re: LTSpice model for a SiC MOSFET8legg
20 May16:44 i  i   +* Re: LTSpice model for a SiC MOSFET4john larkin
20 May18:15 i  i   i`* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May03:42 i  i   i `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May07:46 i  i   i  `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May18:05 i  i   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May13:11 i  i    `* Re: LTSpice model for a SiC MOSFET2legg
21 May16:41 i  i     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May15:04 i  `* Re: LTSpice model for a SiC MOSFET2john larkin
20 May18:25 i   `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
18 May17:03 +- Re: LTSpice model for a SiC MOSFET1legg
18 May17:12 +* Re: LTSpice model for a SiC MOSFET6legg
19 May09:27 i`* Re: LTSpice model for a SiC MOSFET5Bill Sloman
19 May13:48 i `* Re: LTSpice model for a SiC MOSFET4legg
19 May14:12 i  `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
19 May20:28 i   `* Re: LTSpice model for a SiC MOSFET2legg
20 May09:36 i    `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May16:13 +* Re: LTSpice model for a SiC MOSFET26Liz Tuddenham
19 May17:56 i+* Re: LTSpice model for a SiC MOSFET6john larkin
22 May09:44 ii`* Re: LTSpice model for a SiC MOSFET5Liz Tuddenham
22 May15:36 ii `* Re: LTSpice model for a SiC MOSFET4john larkin
22 May16:50 ii  `* Re: LTSpice model for a SiC MOSFET3Liz Tuddenham
22 May17:50 ii   `* Re: LTSpice model for a SiC MOSFET2john larkin
23 May10:04 ii    `- Re: LTSpice model for a SiC MOSFET1Liz Tuddenham
20 May09:46 i`* Re: LTSpice model for a SiC MOSFET19Bill Sloman
20 May10:58 i +* Re: LTSpice model for a SiC MOSFET8Liz Tuddenham
20 May18:34 i i`* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May12:05 i i `* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
21 May13:44 i i  +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May14:19 i i  i`* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
21 May16:51 i i  i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May15:41 i i  `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May18:55 i i   `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May18:47 i `* Re: LTSpice model for a SiC MOSFET10KevinJ93
21 May08:20 i  `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
22 May02:20 i   `* Re: LTSpice model for a SiC MOSFET8KevinJ93
22 May09:12 i    `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
22 May11:43 i     `* Re: LTSpice model for a SiC MOSFET6piglet
22 May14:41 i      +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
22 May19:46 i      i`* Re: LTSpice model for a SiC MOSFET2piglet
23 May06:17 i      i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
22 May15:42 i      `* Re: LTSpice model for a SiC MOSFET2john larkin
22 May17:28 i       `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May19:35 `* Re: LTSpice model for a SiC MOSFET4Edward Rawde
20 May08:54  `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
20 May15:28   `* Re: LTSpice model for a SiC MOSFET2Edward Rawde
20 May18:42    `- Re: LTSpice model for a SiC MOSFET1Bill Sloman

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