Re: LTSpice model for a SiC MOSFET

On Tue, 27 May 2025 01:07:36 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 26/05/2025 4:20 am, JM wrote:

On Mon, 19 May 2025 12:23:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 

On 19/05/2025 12:15 am, john larkin wrote:

On Sun, 18 May 2025 18:11:58 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

>

The drain swing is actually 1.67 times the supply voltage, but it does

 
Where does 1.67 come from?

>
Integrate a series of half-sine peaks that get to 1.67V and the voltage
averages to about 1V.
>
You can do it as purely mathematical exercise, and I did it years ago,
and that's roughly the result I got.
>
There's a voltage drop across the switching FET that's on and the
Baxandall circuit doesn't product perfect half-sine waves, so it hasn't
got a lot to do with precise reality, but it's good enough for
preliminary design.
>
If senile dementia hasn't set in too far I could probably do it again.

Yes, but thats the centre tap voltage.  Due to the autotransformer
action the stress across the off transistor will be twice that, or
1000*PI in this application.  The 1700 volt device under consideration
isn't up to the task.