Re: LTSpice model for a SiC MOSFET

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Sujet : Re: LTSpice model for a SiC MOSFET
De : bill.sloman (at) *nospam* ieee.org (Bill Sloman)
Groupes : sci.electronics.design
Date : 26. May 2025, 17:43:41
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <10125nu$237ha$1@dont-email.me>
References : 1 2 3 4 5 6
User-Agent : Mozilla Thunderbird
On 27/05/2025 1:57 am, JM wrote:
On Tue, 27 May 2025 01:07:36 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 
On 26/05/2025 4:20 am, JM wrote:
On Mon, 19 May 2025 12:23:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>
On 19/05/2025 12:15 am, john larkin wrote:
On Sun, 18 May 2025 18:11:58 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>
The drain swing is actually 1.67 times the supply voltage, but it does
>
Where does 1.67 come from?
>
Integrate a series of half-sine peaks that get to 1.67V and the voltage
averages to about 1V.
>
You can do it as purely mathematical exercise, and I did it years ago,
and that's roughly the result I got.
>
There's a voltage drop across the switching FET that's on and the
Baxandall circuit doesn't product perfect half-sine waves, so it hasn't
got a lot to do with precise reality, but it's good enough for
preliminary design.
>
If senile dementia hasn't set in too far I could probably do it again.
 Yes, but that's the centre tap voltage.  Due to the autotransformer
action the stress across the off transistor will be twice that, or
1000*PI in this application.  The 1700 volt device under consideration
isn't up to the task.
It took me a while to wake up to that. I think that there's an option where you'd use four switching transistors, two to alternately ground either end of the main inductor and two more to alternately switch the feed inductor into the other end of the main inductor, but I haven't worked it out in any detail. It's very much in the brainstorm state at the moment
I have found a 4.5KV MOSFET, the IXYS IXTT02450HV which could survive in the standard Baxandall configuration.
It's $US45.24 each in small volume (which really is excessively expensive), and I've asked for Spice model, but if Infineon is anything to go by, I'm not going to get it anytime soon.
If either Spice model shows up I'll try and put a simulation together. It has nearly got to the point where I should try and bodge a MOSFET model that I have got access to into something that would fit one or other data sheet, but that's hard work, and my model isn't going to be all that trustworthy.
--
Bill Sloman, Sydney

Date Sujet#  Auteur
18 May 25 * LTSpice model for a SiC MOSFET114Bill Sloman
18 May 25 +* Re: LTSpice model for a SiC MOSFET62john larkin
19 May 25 i`* Re: LTSpice model for a SiC MOSFET61Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET34john larkin
19 May 25 i i`* Re: LTSpice model for a SiC MOSFET33Bill Sloman
19 May 25 i i +* Re: LTSpice model for a SiC MOSFET16john larkin
19 May 25 i i i`* Re: LTSpice model for a SiC MOSFET15Bill Sloman
19 May 25 i i i `* Re: LTSpice model for a SiC MOSFET14Edward Rawde
19 May 25 i i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i i  `* Re: LTSpice model for a SiC MOSFET11Bill Sloman
20 May 25 i i i   `* Re: LTSpice model for a SiC MOSFET10Mike Perkins
20 May 25 i i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i i     `* Re: LTSpice model for a SiC MOSFET [OT]8Liz Tuddenham
21 May 25 i i i      `* Re: LTSpice model for a SiC MOSFET [OT]7legg
21 May 25 i i i       +* Re: LTSpice model for a SiC MOSFET [OT]5Liz Tuddenham
21 May18:16 i i i       i`* Re: LTSpice model for a SiC MOSFET [OT]4john larkin
21 May18:51 i i i       i +* Re: LTSpice model for a SiC MOSFET [OT]2Phil Hobbs
21 May19:19 i i i       i i`- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
21 May21:14 i i i       i `- Re: LTSpice model for a SiC MOSFET [OT]1Liz Tuddenham
21 May 25 i i i       `- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
19 May 25 i i `* Re: LTSpice model for a SiC MOSFET16Edward Rawde
19 May 25 i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i  `* Re: LTSpice model for a SiC MOSFET13Bill Sloman
20 May 25 i i   `* Re: LTSpice model for a SiC MOSFET12Edward Rawde
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1John R Walliker
20 May 25 i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i     `* Re: LTSpice model for a SiC MOSFET8Edward Rawde
21 May 25 i i      `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i       `* Re: LTSpice model for a SiC MOSFET6Edward Rawde
21 May 25 i i        +- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i        `* Re: LTSpice model for a SiC MOSFET4john larkin
21 May 25 i i         +* Re: LTSpice model for a SiC MOSFET2Edward Rawde
21 May18:52 i i         i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May18:49 i i         `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET20legg
19 May 25 i i+* Re: LTSpice model for a SiC MOSFET11Bill Sloman
19 May 25 i ii`* Re: LTSpice model for a SiC MOSFET10legg
20 May 25 i ii `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i ii  `* Re: LTSpice model for a SiC MOSFET8legg
20 May 25 i ii   +* Re: LTSpice model for a SiC MOSFET4john larkin
20 May 25 i ii   i`* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii   i `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May 25 i ii   i  `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i ii   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii    `* Re: LTSpice model for a SiC MOSFET2legg
21 May 25 i ii     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET8john larkin
20 May 25 i i `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
26 May11:17 i i  `* Re: LTSpice model for a SiC MOSFET6Cursitor Doom
26 May14:44 i i   +* Re: LTSpice model for a SiC MOSFET2john larkin
26 May15:55 i i   i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
26 May15:49 i i   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
26 May22:51 i i    `* Re: LTSpice model for a SiC MOSFET2Cursitor Doom
27 May05:29 i i     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
25 May19:20 i `* Re: LTSpice model for a SiC MOSFET6JM
26 May16:07 i  `* Re: LTSpice model for a SiC MOSFET5Bill Sloman
26 May16:57 i   `* Re: LTSpice model for a SiC MOSFET4JM
26 May17:43 i    `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
27 May19:09 i     `* Re: LTSpice model for a SiC MOSFET2JM
28 May16:16 i      `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
18 May 25 +- Re: LTSpice model for a SiC MOSFET1legg
18 May 25 +* Re: LTSpice model for a SiC MOSFET6legg
19 May 25 i`* Re: LTSpice model for a SiC MOSFET5Bill Sloman
19 May 25 i `* Re: LTSpice model for a SiC MOSFET4legg
19 May 25 i  `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
19 May 25 i   `* Re: LTSpice model for a SiC MOSFET2legg
20 May 25 i    `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 +* Re: LTSpice model for a SiC MOSFET35Liz Tuddenham
19 May 25 i+* Re: LTSpice model for a SiC MOSFET7john larkin
22 May09:44 ii`* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
22 May15:36 ii `* Re: LTSpice model for a SiC MOSFET5john larkin
22 May16:50 ii  `* Re: LTSpice model for a SiC MOSFET4Liz Tuddenham
22 May17:50 ii   `* Re: LTSpice model for a SiC MOSFET3john larkin
23 May10:04 ii    `* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
23 May14:54 ii     `- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i`* Re: LTSpice model for a SiC MOSFET27Bill Sloman
20 May 25 i +* Re: LTSpice model for a SiC MOSFET8Liz Tuddenham
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i `* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
21 May 25 i i  +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i i  i`* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
21 May16:51 i i  i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i  `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May18:55 i i   `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i `* Re: LTSpice model for a SiC MOSFET18KevinJ93
21 May 25 i  `* Re: LTSpice model for a SiC MOSFET17Bill Sloman
22 May02:20 i   `* Re: LTSpice model for a SiC MOSFET16KevinJ93
22 May09:12 i    +* Re: LTSpice model for a SiC MOSFET8Bill Sloman
22 May11:43 i    i`* Re: LTSpice model for a SiC MOSFET7piglet
22 May14:41 i    i +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
22 May19:46 i    i i`* Re: LTSpice model for a SiC MOSFET2piglet
23 May06:17 i    i i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
22 May15:42 i    i +* Re: LTSpice model for a SiC MOSFET2john larkin
22 May17:28 i    i i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
23 May15:26 i    i `- Re: LTSpice model for a SiC MOSFET1legg
27 May00:09 i    `* Re: LTSpice model for a SiC MOSFET7john larkin
27 May05:37 i     `* Re: LTSpice model for a SiC MOSFET6Bill Sloman
27 May14:16 i      `* Re: LTSpice model for a SiC MOSFET5Liz Tuddenham
19 May 25 +* Re: LTSpice model for a SiC MOSFET4Edward Rawde
27 May15:02 `* Re: LTSpice model for a SiC MOSFET5Joe Gwinn

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