Re: Hypothetical possibilities

Liste des GroupesRevenir à theory 
Sujet : Re: Hypothetical possibilities
De : mikko.levanto (at) *nospam* iki.fi (Mikko)
Groupes : comp.theory
Date : 22. Jul 2024, 12:05:10
Autres entêtes
Organisation : -
Message-ID : <v7led6$kacj$1@dont-email.me>
References : 1
User-Agent : Unison/2.2
On 2024-07-20 15:28:31 +0000, olcott said:

void DDD()
{
   HHH(DDD);
}
 int main()
{
   DDD();
}
 (a) Termination Analyzers / Partial Halt Deciders must halt
this is a design requirement.
For a partial analyzer or deciders this is not always required.

(b) Every simulating termination analyzer HHH either
aborts the simulation of its input or not.
This must be interpreted to mean that a simulating termination analyzer
may abort its simulation for some simulated abort and simulate others
to the termination.

(c) Within the hypothetical case where HHH does not abort
the simulation of its input {HHH, emulated DDD and executed DDD}
never stop running.
The case is not very hypothetical. Given the HHH you already have,
it is fairly easy to construct the "hypothetical" HHH and see what
it actually does.

This violates the design requirement of (a) therefore HHH must
abort the simulation of its input.
The violation simply means that the "hypothetical" HHH is not a
termination analyzer of partial halt decider in sense (a). What
it "must" be or do depends on the requirements.
--
Mikko

Date Sujet#  Auteur
1 Jul 25 o 

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