Re: How Partial Simulations correctly determine non-halting ---Should I quit Richard at this point?

On 6/9/24 12:38 AM, olcott wrote:

On 6/8/2024 11:11 PM, Richard Damon wrote:

On 6/9/24 12:02 AM, olcott wrote:

On 6/8/2024 10:53 PM, Richard Damon wrote:

On 6/8/24 10:58 PM, olcott wrote:

Are you asking how does infinite recursion terminate normally?

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No, are you THAT stupid?
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I only missed Mensa by one point I am in the top 97%
I was also top in several of my computer science classes.

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Then why ard you so ignorant of thing you claim to know something about?
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I am asking how the x86 processor gets from calling HH(DD,DD) back to the begining of DD as code actually executed, so it shows up in the simulation of the HH that was simulating that DD.
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When the HH that this DD calls starts it simulation, since you have stated this is done by pure emulation, when did the program counter for that thread of execution ever get set back to the begining of DD.
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Note, NOT the "virtual program counter that the simulator being simulated was using in its simulation (since that isn't anywhere in your definition of correct simulation) but the actual Program Counter in the simulation being run get there?
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*See if this explains it*
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_DD()
[00001c22] 55         push ebp
[00001c23] 8bec       mov ebp,esp
[00001c25] 51         push ecx
[00001c26] 8b4508     mov eax,[ebp+08]
[00001c29] 50         push eax      ; push DD 1c22
[00001c2a] 8b4d08     mov ecx,[ebp+08]
[00001c2d] 51         push ecx      ; push DD 1c22
[00001c2e] e80ff7ffff call 00001342 ; call HH
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A {correct simulation} means that each instruction of the
above x86 machine language of DD is correctly simulated
by HH and simulated in the correct order.
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In other words the first seven steps of DD correctly simulated
by HH call HH(DD,DD) to repeat these first seven steps. HH then
simulates itself simulating DD until this second instance of DD
calls another HH(DD,DD) to repeat these first seven steps again.

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But by the first paragraph,

 The first paragraph is the overall gist of what is happening.

So your first paragraph isn't a stipulation defining what a correct simulation means for you?
IF you aren't stipulating a definition of Correct Simulation, then you get the canonical definition, which HH fails at meeting or answering about.

The second paragraph gets into specific details.
 

the exectution of the seventh instruction, leaves the program counter at 00001C2E, so by the rule of correctly simulated in the correct order, the only allowed instruction to simulate next is the call HH at 00001C2E.
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 I have explained how HH simulates itself several times now.
[00001c2e] e80ff7ffff call 00001342 ; call HH
Call the actual HH at 00001342

Right, so the SIMULATION needs to do that, and a simulation that follows the code into HH will NEVER get to seeing it simulation reach the beginning of DD again.
I guess you are just showing you don't actually know how the x86 processor (or any processor) actually works, or what it means, even in general, to correctly simulate something.
Say Bye-Bye to the validity of all your work.

 

EXPLAIN HOW THAT IS NOT RIGHT, Reference the document which shows your idea is an actual correct simulation of the x86 instruction.
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Then when we simulate the CALL 00001342 instruction, that leaves the program counter at 00001362, o by te rules of correctly simulated in the correct order, the only alloed instruction to simulate next is the instruction at 00001362.
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Again, EXPLAIN HOW THAT IS NOT RIGHT, Reference the document which shows your idea is an actual correct simulation of the x86 instruction.
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That is the EXACT behavior specified by those instructions, so ANY other behavior is NOT a "correct simulaition of the instruction" and going to any other instruction other than the one the Program Counter current points to is not in the correct order.
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Until you answer, any other remarks will get answered by the fact that you have been caught in a falsehood, and are trying to do a dishonest dodge to get out of handling it.
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Since you have admitted to falsifing your verification, you are going to have to actual show your information.
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*I have proved this point since three years ago*
On 5/29/2021 2:26 PM, olcott wrote:
[Would the simulation of D be infinitely nested unless simulating partial halt decider H terminated its simulation of D?]
Message-ID: <YJKdnZg9v__rCC_9nZ2dnUU7-QXNnZ2d@giganews.com>
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Not the quesiton being asked, which is par for the course with you.
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Remember, you just admitted to claiming verification with an output you didn't actually look at closely, so nothing "verified" by you can be considered verified.
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You have burnt that bridge, you are going to need to provide the "paperwork" for the things you claim to be verified.
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We can get to that question later, once we get your simulations to actually meet your specifications, which they currently do not.
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Seems strange that a programmer with the qualifications you have claimed would have missed such an obvious error, I guess you just never check your work.
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