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On 6/9/2024 8:07 PM, Richard Damon wrote:But saying that you had looked at it and that is shows something that it doesn/t isn't a "mistake", but a reckless disregard for the truth.On 6/9/24 8:50 PM, olcott wrote:I never even looked that the trace untilOn 6/9/2024 7:36 PM, Richard Damon wrote:>On 6/9/24 8:17 PM, olcott wrote:>On 6/9/2024 1:08 PM, Richard Damon wrote:>On 6/9/24 10:04 AM, olcott wrote:On 6/9/2024 4:33 AM, Mikko wrote:On 2024-06-08 13:06:06 +0000, olcott said:>
>On 6/8/2024 1:58 AM, Mikko wrote:>On 2024-06-07 18:41:47 +0000, olcott said:>
>On 6/7/2024 1:24 PM, Richard Damon wrote:>On 6/7/24 2:02 PM, olcott wrote:>On 6/7/2024 12:50 PM, Alan Mackenzie wrote:>[ Followup-To: set ]>
>
In comp.theory olcott <polcott333@gmail.com> wrote:
>
[ .... ]
>_DD()>
[00001e12] 55 push ebp
[00001e13] 8bec mov ebp,esp
[00001e15] 51 push ecx
[00001e16] 8b4508 mov eax,[ebp+08]
[00001e19] 50 push eax ; push DD
[00001e1a] 8b4d08 mov ecx,[ebp+08]
[00001e1d] 51 push ecx ; push DD
[00001e1e] e85ff5ffff call 00001382 ; call HHA {correct simulation} means that each instruction of the>
above x86 machine language of DD is correctly simulated
by HH and simulated in the correct order.
That's a bit of sudden and substantial change, isn't it? Less than a few
days ago, you were defining a correct simulation as "1 to N instructions"
simulated (without ever specifying what you meant by N). It seems that
the simulation of exactly one instruction would have met your criterion.
>
That now seems to have changed.
>
Because I am a relatively terrible writer I must constantly
improve my words on the basis of reviews.
>
Try to show how this DD correctly simulated by any HH ever
stops running without having its simulation aborted by HH.
>
_DD()
[00001e12] 55 push ebp
[00001e13] 8bec mov ebp,esp
[00001e15] 51 push ecx
[00001e16] 8b4508 mov eax,[ebp+08]
[00001e19] 50 push eax ; push DD
[00001e1a] 8b4d08 mov ecx,[ebp+08]
[00001e1d] 51 push ecx ; push DD
[00001e1e] e85ff5ffff call 00001382 ; call HH
>
A {correct simulation} means that each instruction of the
above x86 machine language of DD is correctly simulated
by HH and simulated in the correct order.
>
Anyone claiming that HH should report on the behavior
of the directly executed DD(DD) is requiring a violation
of the above definition of correct simulation.
>
And thus you admit that HH is not a Halt Decider,
More dishonest deflection.
The point that I made and you try to deflect using the strawman
deception as a fake rebuttal is the I just proved that DD is correctly
simulated by HH and this is not the same behavior as the directly
executed DD(DD).
The true point is that you have never shown any proof about simulation
by HH.
In other words you lack the mandatory prerequisites so the
correct proof only looks like gibberish to you.
Hard to teest wihout the correct proof.
>
Anyway, something that starts with "Proof:" and ends with "Q.E.D." may
fail to be a proof. It depends on what is between.
>
typedef void (*ptr)(); // pointer to void function
>
void HHH(ptr P, ptr I)
{
P(I);
return;
}
>
void DDD(int (*x)())
{
HHH(x, x);
return;
}
>
int main()
{
HHH(DDD,DDD);
}
>
In the above Neither DDD nor HHH ever reach their own return
statement thus never halt.
>
V V V So, what does this mean???? (see comment below) V V V
>>>When HHH is a simulating halt decider then HHH sees that>
DDD correctly simulated by HHH cannot possibly reach its
own return statement, AKA
But HHH (as shown above) ISN'T a simulating halt decider, so you are just caught in another of youre lies.
>
I didn't say it was a simulating halt decider. I needed to see
if my reviewers understand what infinite recursion is before
proceeding with them. It looks like they do not understand this.
The why did you say "When HHH is a simulating Halt Decider..."
>
You can't use the same name in the same arguememt to mean different things!
>
SO of course you are implying that your HHH above is to be thought of as a Simulating Halting Decider, or at least that it will behave as one.
>>>
That you call everything that I say a lie even when it
is not even incorrect is ridiculously childish of you.
>
Because most things you say are a lie, because you just don't know what you are saying.
>
I told one exaggeration five years ago.
I said that I had a Turing machine believing that what I
had was equivalent to a Turing machine, not yet knowing
that anyone understood Turing equivalence.
NO, you have told many more lies than that.
>
For instance, you said that you system produced a 250 page trace that you verified that it showed a property of H, when it turns out you barely glanced at it and didn't even realizd it wasn't the trace you thought it was.
>
OBVIOUSLY you lied that you studied that trace.
>
after you looked at it. Calling mistakes
lies IS DEFAMATION IN YOUR STATE
Nope.You LIE that your published traces are "Correct Simulations" per the x86 instructions shown, when they clearly can not be, as a call H would then be followed by the code in H, which it isn't.IT AM STOPPING RIGHT HERE
>
*THAT D IS CORRECTLY SIMULATED BY H HAS BEEN PROVED FOR THREE YEARS*
THE COMPLETE PROOF OF THIS IS THAT THE X86 SOURCE-CODENot a proof. and it doesn't.
OF D EXACTLY MATCHES THE PROVIDED TRACES
On 5/29/2021 2:26 PM, olcott wrote:THEN STOP LYING.
[Would the simulation of D be infinitely nested unless simulating partial halt decider H terminated its simulation of D?]
https://groups.google.com/g/comp.theory/c/dTvIY5NX6b4/m/cHR2ZPgPBAAJ
THIS IS AN OFFICIAL CEASE AND DESIST NOTIFICATION.
STOP CALLING ME A LIAR.
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