Re: Parallel Forth on a 44 core machine

mhx@iae.nl (mhx) writes:

What I meant is severe slowdown when reading variables that are
physically *close* to variables that belong to another process.

That is known as false sharing.  The cache coherence protocols work at
the granularity of a a cache line (usually 64 bytes).  If core A
writes to a variable, and core B, say, reads one in the same cache
line, the cache coherence protocol first makes that cache line
modified by core A (and every other core has to invalidate that cache
line), and then core B has to wait until core A sends out the data to
the other cores.

It happens for both AMD and Intel on both Windows and Linux.
Spacing such variables farther apart has dramatic impact but
is quite inconvenient in most cases.

Yes, but if you want performance, you have to rearrange your data to
avoid false sharing.

I don't recall that transputers had these problems.

Transputers have no shared memory and therefore no cache coherence
protocols.

- anton
--
M. Anton Ertl  http://www.complang.tuwien.ac.at/anton/home.html
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