Re: Locals revisited

Paul Rubin <no.email@nospam.invalid> writes:

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

There is the E subspecification of the RISC-V specification with 16
registers.  I don't know if anybody has implemented this.

>
The CH32V003 uses it and is of some interest as a Forth target.  It has
16k of flash and 2k of ram.

Interesting.  But with 2KB of RAM, one is even less likely to want to
use so many stack pointers than in less restricted settings.  One
probably just wants to use a data and a return stack, that's all.

https://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/

I see no mention of RV32E here, but searching further, I see

https://wch-ic.com/downloads/CH32V003DS0_PDF.html

which says "RV32EC instruction set".

https://dl.acm.org/doi/10.1145/3578360.3580261 indicates some minor
speed differences, not always favorable.

The abstract says:

|Binaries compiled for better compression show changes in their
|execution time of at most ± 1.5 %. We analyze these against LLVM’s
|spilling metrics, and conclude that the effect is probably not
|systemic but a random fluctuation in the register allocation
|heuristic.

This sounds like what someone (Preston Briggs?) called IIRC
"NP-completeness noise" (or something along these lines).  The idea is
that optimal register allocation is an NP-complete problem, so we use
heuristics to get a good, but not necessarily optimal solution.  Some
of the decisions taken may lead to more suboptimality than others, and
that's what the creator of the term saw.

However, the performance effects may also be due to other effects that
have little to do with register allocation itself, such as the effects
of branch target alignment relative to instruction fetch granularity
units, and of instructions straddling the fetch granularity boundaries
or not.

In any case, this work more supports than contradicts my statement
"typically the same speed".

- anton
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