Sujet : Re: Parsing timestamps?
De : anton (at) *nospam* mips.complang.tuwien.ac.at (Anton Ertl)
Groupes : comp.lang.forthDate : 02. Jul 2025, 16:44:40
Autres entêtes
Organisation : Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID : <2025Jul2.174440@mips.complang.tuwien.ac.at>
References : 1 2 3 4 5 6 7 8 9 10 11
User-Agent : xrn 10.11
minforth <
minforth@gmx.net> writes:
Today, you could go insane if you had to write assembler code
with SSE1/2/3/4/AVX/AES etc. extended CPU commands (or take GPU
programming...)
>
Even chip manufacturers provide C libraries with built-ins and
intrinsics to handle this complexity, and optimising C compilers
for selecting the best operations.
Not really. Each AVX intrinsic corresponds to an instruction, and I
expect the compiler to produce that instruction. The benefit of the
intrinsics is that you can mix this assembly language with C code, and
the C compiler will do the register allocation for you, but normally
not a "better" operation. That being said, I have seen a case where
an AVX256 intrinsic was translated to two AVX128 or SSE2 instructions
because that sequence was suppsed to be faster on some Intel CPU (and
it's Intel who writes the code for AVX intrinsics).
In any case, given that there is one intrinsic for each SIMD
instruction, you go just as insane with the plethora of intrinsics as
with the plethora of SIMD instructions.
The C way to dealing with SIMD instructions is auto-vectorization. It
does not work particularly well, however, but given that it works on
existing benchmarks, it has an unsurmountable advantage over explicit
(manual) vecorization.
- anton
-- M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.htmlcomp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html New standard: https://forth-standard.org/EuroForth 2023 proceedings: http://www.euroforth.org/ef23/papers/EuroForth 2024 proceedings:
http://www.euroforth.org/ef24/papers/