Re: The future. (was Re: Parsing timestamps?)

Reminds me of the 6502 for some reason.  But it's the 'skip next
instruction on bit in register' that throws me.

Nothing too unusual. It's actually just an abbreviation
for something like, for example:
 CMP AX, BX
 JZ SHORT skip
 CALL something
skip: ...
So instead of separate CMP and JZ we've got
"CMP?JZ" as single instruction. If not the
variable size of instruction in x86, one could
devise a macro. On a second thought: probably
in A86 it'll be possible to devise such a macro,
because its macro facility treats macro
parameters character-wise. So probably a macro
like 'CMP?JZ reg1,reg2 next_instruction" should
be possible (I'll try that later).
PIC features similar instructions (INCFSZ/DECFSZ).
PIC is actually more 6502-like, with its spartan
instruction set (when compared to ATMEL).

Didn't get that in the good old days as products were expected to
have a reasonable lifetime.  Today CPU designs are as 'throw away'
as everything else.  No reason to believe RISC-V will be different.
Only thing distinguishing it are the years of hype and promise.

Well, at least x86 and ARM seem to be more 'persistent'.
Actually they already proved to be.
--