Sujet : Re: The future. (was Re: Parsing timestamps?)
De : dxforth (at) *nospam* gmail.com (dxf)
Groupes : comp.lang.forthDate : 17. Jul 2025, 06:55:41
Autres entêtes
Organisation : i2pn2 (i2pn.org)
Message-ID : <9281c7c64154e5978fbf7bd0d90bde6b4a4a0ce9@i2pn2.org>
References : 1 2 3 4 5 6 7 8 9
User-Agent : Mozilla Thunderbird
On 16/07/2025 6:25 pm, LIT wrote:
It depends on how many are being programmed by the likes of GCC.
When ATMEL hit the market the manufacturer claimed their chips
were designed with compilers in mind. Do Arduino users program
in hand-coded assembler? Do you? It's no longer just the chip's
features and theoretical performance one has to worry about but
the compilers too.
Regarding features it's worth to mention
that ATMELs actually are quite nice to
program them in ML. Even, if they were
designed "with compilers in mind".
...
Reminds me of the 6502 for some reason. But it's the 'skip next
instruction on bit in register' that throws me. Not to mention
companies that release chips that don't do what the spec says.
Their solution? Amend the documentation to exclude that feature!
Didn't get that in the good old days as products were expected to
have a reasonable lifetime. Today CPU designs are as 'throw away'
as everything else. No reason to believe RISC-V will be different.
Only thing distinguishing it are the years of hype and promise.